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19-4438; Rev 0; 1/09
KIT ATION EVALU E AILABL AV
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
General Description Features
o Dual-/Single-Phase Interleaved Quick-PWM Controller o 0.5% VOUT Accuracy Over Line, Load, and Temperature o 7-Bit IMVP6+ DAC o Dynamic Phase Selection Optimizes Active/Sleep Efficiency o Transient Phase Overlap Reduces Output Capacitance o Active Voltage Positioning with Adjustable Gain o Accurate Lossless Current Balance o Accurate Droop and Current Limit o Remote Output and Ground Sense o Adjustable Output Slew-Rate Control o Power-Good Window Comparator o Power Monitor o Programmable Thermal-Fault Protection o Phase Fault Output (PHASEGD) o Drives Large Synchronous Rectifier FETs o 4.5V to 26V Battery Input Range o Output Overvoltage and Undervoltage Protection o Soft-Startup and Soft-Shutdown o Integrated Boost Switches o Low-Profile 7mm x 7mm, 48-Pin TQFN Package
MAX17410
The MAX17410 is a 2-/1-phase interleaved QuickPWMTM step-down VID power-supply controller for notebook IMVP6+ CPUs. True out-of-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17410 is intended for two different CPU core applications: either bucking down the battery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. A power monitor provides a buffered analog voltage output proportional to the power delivered to the load. The MAX17410 is available in a 48-pin, 7mm x 7mm TQFN package.
Applications
IMVP6+ Core Supply
PGND1 BST1 DH1 DL1 VDD LX1
Pin Configuration
BST2 DH2 N.C. DL2 LX2
Multiphase CPU Core Supply Voltage-Positioned, Step-Down Converters Notebook/Desktop Computers
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25 D0 D1 D2 D3 D4 37 38 39 40 41 42 43 44 45 46 47 48 1 PWRGD 2 PSI 3 PMON 4 THRM 5 VRHOT 6 NTC 7 PHASEGD 8 PGDIN 9 FB 10 11 12 SGND TIME VPS 24 23 22 21 20 19 CSP1 CSP2 VCC GND IN CSPAVG CSN1 CSN2 CCI GNDS OUTS ILIM
Ordering Information
PART TEMP RANGE PIN-PACKAGE MAX17410GTM+ -40C to +105C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package.
D5 D6 SHDN DPRSLPVR DPRSTP CLKEN V3P3
MAX17410
PGND2
18 17 16 15 14 13
*EP = Exposed pad.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
ABSOLUTE MAXIMUM RATINGS
VCC, VDD, V3P3 to GND ...........................................-0.3V to +6V D0-D6, PSI, DPRSLPVR, DPRSTP to GND ..............-0.3V to +6V CSPAVG, CSP_, CSN_, ILIM to GND .......................-0.3V to +6V PWRGD, PHASEGD, VRHOT to GND ......................-0.3V to +6V FB, OUTS, CCI, TIME, PMON to GND........-0.3V to (VCC + 0.3V) PGDIN, NTC, THRM to GND ......................-0.3V to (VCC + 0.3V) CLKEN to GND..........................................-0.3V to (V3P3 + 0.3V) VPS to OUTS .........................................................-0.3V to +0.3V SHDN to GND (Note 1)...........................................-0.3V to +30V IN to GND ...............................................................-0.3V to +30V GNDS, SGND, PGND_ to GND .............................-0.3V to +0.3V DL_ to GND ................................................-0.3V to (VDD + 0.3V) BST_ to VDD............................................................-0.3V to +30V LX_ to BST_ ..............................................................-6V to +0.3V DH_ to LX_ ...............................................-0.3V to (VBST - +0.3V) Continuous Power Dissipation (48-pin, 7mm x 7mm TQFN) Up to +70C ..............................................................2222mW Derating Above +70C ..........................................27.8mW/C Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10s) .................................+300C
Note 1: SHDN may be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWM CONTROLLER VCC, VDD Input Voltage Range V3P3 IN Measured at FB with respect to GNDS, includes load regulation error (Note 2) DAC codes from 0.8125V to 1.5000V DAC codes from 0.3750V to 0.8000V DAC codes from 0 to 0.3625V 4.5 3.0 4.5 -0.5 -7 -20 1.192 VCC = 4.5V to 5.5V, VIN = 4.5V to 26V VPS floating, TA = +25C -0.1 3.5 -200 A GNDS IGNDS VTIME VOUT/ VGNDS V(OUTS, GNDS) = 1.0V RTIME = 71.5k 0.97 -15 1.985 1.00 -10 2.000 10 2.5 +200 1.03 -4 2.015 mV V/V A V 1.200 0.1 +0.1 40 5.5 3.6 26 +0.5 +7 mV +20 1.209 V % A % V SYMBOL CONDITIONS MIN TYP MAX UNITS
DC Output Voltage Accuracy
VOUT
Boot Voltage Line Regulation Error OUTS Input Bias Current OUTS-to-VPS Resistance SGND-to-AGND Resistance GNDS Input Range GNDS Gain GNDS Input Bias Current TIME Regulation Voltage
VBOOT
2
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL RTIME = 71.5k CONDITIONS (12.5mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) TIME Slew-Rate Accuracy Soft-start and soft-shutdown: RTIME = 35.7k (3.125mV/s nominal) to 178k (0.625mV/s nominal) Slow: VDPRSTP = VDPRSLPVR = 5V, 1/4 normal slew rate, RTIME = 35.7k (6.25mV/s nominal) to 178k (1.25mV/s nominal) On-Time Accuracy Minimum Off-Time BIAS CURRENTS Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Supply Current (V3P3) Quiescent Supply Current (IN) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Supply Current (V3P3) Shutdown Supply Current (IN) FAULT PROTECTION Skip mode after output reaches the regulation voltage or PWM mode, measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB Minimum OVP threshold; measured at FB Output OvervoltagePropagation Delay t OVP FB forced 25mV above trip threshold ICC IDD I3P3 I IN ICC,SDN IDD,SDN I3P3,SDN IIN,SDN Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point Measured at VDD, VDPRSLPVR = 0, FB forced above the regulation point, TA = +25C Measured at V3P3, FB forced within the CLKEN power-good window, TA = +25C Measured at IN, VIN = 10V Measured at VCC, SHDN = GND, TA = +25C Measured at VDD, SHDN = GND, TA = +25C Measured at V3P3, SHDN = GND, TA = +25C Measured at IN, VIN = 26V, SHDN = GND, VCC = 0V or 5V, TA = +25C 3 0.02 0.01 15 0.01 0.01 0.01 0.01 6 1 1 25 1 1 1 0.1 mA A A A A A A A t ON t OFF(MIN) VIN = 10V, VFB = 1.0V, VCCI = (1.0V + VDIODE), measured at DH_, 300kHz per phase nominal (Note 3) Measured at DH_ (Note 3) MIN -10 -15 TYP MAX +10 +15 UNITS
MAX17410
-16
+30
%
-12
+25
300
333 300
366 375
ns ns
250
300
350
mV
Output OvervoltageProtection Threshold
VOVP
1.75
1.80 0.8 10
1.85
V
s
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3
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output UndervoltageProtection Threshold Output UndervoltagePropagation Delay CLKEN Startup Delay and Boot Time Period PWRGD Startup Delay SYMBOL VUVP tUVP tBOOT CONDITIONS Measured at FB with respect to the voltage target set by the VID code; see Table 4 FB forced 25mV below trip threshold Measured from the time when FB reaches the boot target voltage (Note 2) Measured at startup from the time when CLKEN goes low Measured at FB with respect to the voltage target set by the VID code; see Table 4, 20mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) 20 3 MIN -450 TYP -400 10 60 6.5 100 10 MAX -350 UNITS mV s s ms
-350
-300
-250 mV
CLKEN and PWRGD Threshold
+150
+200
+250
CLKEN and PWRGD Delay PHASEGD Delay CLKEN, PWRGD, and PHASEGD Transition Blanking Time (VID Transitions) PHASEGD Transition Blanking Time (Phase 2 Enable Transitions) CLKEN Output Low Voltage CLKEN Output High Voltage PWRGD, PHASEGD Output Low Voltage PWRGD, PHASEGD Leakage Current CSN_ Pulldown Resistances in Shutdown VCC Undervoltage-Lockout Threshold THERMAL PROTECTION THRM, NTC Pullup Current Ratio of NTC Pullup Current to THRM Pullup Current VUVLO(VCC)
FB forced 25mV outside the PWRGD trip thresholds V(CCI, FB) forced 25mV outside trip thresholds tBLANK Measured from the time when FB reaches the target voltage (Note 2) Number of DH2 pulses for which PHASEGD is blanked after phase 2 is enabled Low state, ISINK = 3mA High state, I SOURCE = 3mA Low state, I SINK = 3mA High-impedance state; PWRGD, PHASEGD forced to 5V; TA = +25C SHDN = 0, measured after soft-shutdown completed (DL = low) Rising edge, 65mV typical hysteresis, controller disabled below this level 4.05 V3P3 0.4
10 10
s s
20
s
32 0.4
Pulses V V 0.4 1 V A
10 4.27 4.48 V
ITHRM, INTC VTHRM = VNTC = 1V INTC/ITHRM VTHRM = VNTC = 1V
40 0.995
50 1
60 1.025
A A/A
4
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER VRHOT Trip Threshold VRHOT Delay VRHOT Output On-Resistance VRHOT Leakage Current Thermal-Shutdown Threshold T SHDN SYMBOL CONDITIONS Measured at NTC with respect to THRM, VTHRM = 1V, falling edge; typical hysteresis = 100mV t VRHOT VNTC forced 25mV below VTHRM, VTHRM = 1V, falling edge High-impedance state, VRHOT forced to 5V, TA = +25C Typical hysteresis = 15C VTIME - VILIM = 100mV VLIMIT VCSP_ - VCSN_ VTIME - VILIM = 500mV ILIM = VCC Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSPAVG, CSP_, CSN_ Common-Mode Input Range Phase 2 Disable Threshold CSPAVG, CSP_, CSN_ Input Current ILIM Input Current Droop Amplifier Offset Droop Amplifier Transconductance Gm(FB) Measured at CSP2 ICSPAVG, TA = +25C ICSP_, ICSN_ I ILIM TA = +25C [VCSPAVG - (VCSN1 + VCSN2)/2] at IFB = 0 TA = +25C TA = 0C to +85C VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT VZERO VAGND - VLX_, DPRSLPVR = 5V 0 3 -0.2 -0.1 -0.5 -0.75 1.180 1.2 VCC 1 7 45 20 -4 1 2 VCC 0.4 +0.2 +0.1 +0.5 +0.75 1.216 +160 10 50 22.5 13 55 25 +4 mV mV V V A A mV mS mV MIN -12 TYP MAX +12 UNITS mV
MAX17410
10 2 8 1
s
RON(VRHOT) Low state
A C
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive)
IFB/ [VCSPAVG - (VCSN1 + VCSN2)/2], VFB = VCSN_ = 0.45V to 1.5V [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 500mV
Power Monitor Output Voltage for Typical HFM Conditions
VPMON
V(OUTS, GNDS) = 1.200V, I PMON = 0A
1.65
1.7
1.743 V
0.738
0.765
0.792
Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) Power Monitor Gain Referred to [VCSPAVG - (VCSN1 + VCSN2)/2]
APMON/ VOUT APMON/VCS
[VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = 0A V(CSN, GNDS) = 1.200V, V(TIME, ILIM) = 225mV, I PMON = 0A
1.375 104
1.4167 113.33
1.452 123
V/V V/V
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Power Monitor Load Regulation Current Balance Amplifier Offset Current Balance Amplifier Transconductance GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source Current DH_ Gate-Driver Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Driver Propagation Delay DL_ Transition Time DH_ Transition Time Internal BST_ Switch On-Resistance LOGIC AND I/O Logic Input High Voltage Logic Input Low Voltage Low-Voltage Logic Input High Voltage Low-Voltage Logic Input Low Voltage Logic Input Current VIH VIL VIHLV VILLV SHDN, PGDIN, DPRSLPVR SHDN, PGDIN, DPRSLPVR PSI, D0-D6, DPRSTP PSI, D0-D6, DPRSTP TA = +25C, PGDIN TA = +25C, SHDN, DPRSLPVR, PSI, DPRSTP, D0-D6 = 0 or 5V -1.5 -1 -1 0.67 0.33 -0.5 +1 A 2.3 1.0 V V V V R ON(BST_) R ON(DH_) R ON(DL_) BST_ - LX_ forced to 5V High state (pullup) Low state (pulldown) DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DH_ low to DL_ high DL_ low to DH_ high DL_ falling, CDL_ = 3nF DL_ rising, CDL_ = 3nF DH_ falling, CDH_ = 3nF DH_ rising, CDH_ = 3nF High state (pullup) Low state (pulldown) 0.9 0.7 0.7 0.25 2.2 2.7 2.7 8 20 20 20 20 20 20 10 20 2.5 2.0 2.0 0.7 A A A A ns ns ns Gm(CCI) SYMBOL CONDITIONS Measured at PMON IPMON = 0 to 500A with respect to I PMON = -100A unloaded voltage (VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0 ICCI/ [(VCSP1 - VCSN1) - (VCSP2 - VCSN2)], VCSN_ = 0.45V to 1.5V MIN -6 50 -1.0 200 +1.0 TYP MAX UNITS V/A mV mV S
IDH_(SOURCE) DH_ forced to 2.5V, BST_ - LX_ forced to 5V IDH_(SINK) IDL_(SINK) tDH_DL_ tDL_DH_ IDL_(SOURCE) DL_ forced to 2.5V
6
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = -40C to +105C, unless otherwise noted.)
PARAMETER PWM CONTROLLER VCC, VDD Input Voltage Range V3P3 IN Measured at FB with respect to DAC codes from GNDS, includes 0.3750V to 0.8000V load regulation error (Note 2) DAC codes from 0 to 0.3625V DAC codes from 0.8125V to 1.5000V 4.5 3.0 4.5 -0.75 -10 -25 1.185 3.5 -200 A GNDS IGNDS VTIME VOUT/ VGNDS V(OUTS, GNDS) = 1.0V RTIME = 71.5k RTIME = 71.5k (12.5mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) TIME Slew-Rate Accuracy Soft-start and soft-shutdown: RTIME = 35.7k (3.125mV/s nominal) to 178k (0.625mV/s nominal) Slow: VDPRSTP = VDPRSLPVR = 5V, 1/4 normal slew rate, RTIME = 35.7k (6.25mV/ s nominal) to 178k (1.25mV/s nominal) On-Time Accuracy Minimum Off-Time BIAS CURRENTS Quiescent Supply Current (VCC) Quiescent Supply Current (IN) ICC I IN Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point Measured at IN, VIN = 10V 6 25 mA A t ON t OFF(MIN) VIN = 10V, VFB = 1.0V, VCCI = (1.0V + VDIODE), measured at DH_, 300kHz per phase nominal (Note 3) Measured at DH_ (Note 3) 0.97 -15 1.985 -10 -15 5.5 3.6 26 +0.75 +10 mV +25 1.215 40 +200 1.03 -4 2.015 +10 +15 mV V/V A V V % V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17410
DC Output Voltage Accuracy
VOUT
Boot Voltage OUTS to VPS Resistance GNDS Input Range GNDS Gain GNDS Input Bias Current TIME Regulation Voltage
VBOOT
-16
+30
%
-12
+25
290
333
376 375
ns ns
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7
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = -40C to +105C, unless otherwise noted.)
PARAMETER FAULT PROTECTION Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output has not reached the regulation voltage; measured at FB VUVP tBOOT Measured at FB with respect to the voltage target set by the VID code (see Table 4) Measured from the time when FB reaches the boot target voltage (Note 2) Measured at startup from the time when CLKEN goes low Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) SYMBOL CONDITIONS MIN TYP MAX UNITS
250
350
mV
Output Overvoltage-Protection Threshold
VOVP
1.75
1.85
V
Output Undervoltage-Protection Threshold CLKEN Startup Delay and Boot Time Period PWRGD Startup Delay
-450 20 3
-350 100 10
mV s ms
-350
-250 mV
CLKEN and PWRGD Threshold
+150
+250 0.4 V V 0.4 1 V A V
CLKEN Output Low Voltage CLKEN Output High Voltage PWRGD, PHASEGD Output Low Voltage PWRGD, PHASEGD Leakage Current VCC Undervoltage-Lockout Threshold THERMAL PROTECTION THRM, NTC Pullup Current Ratio of NTC Pullup Current to THRM Pullup Current VRHOT Trip Threshold VRHOT Output On-Resistance ITHRM, INTC INTC/ITHRM VUVLO(VCC)
Low state, ISINK = 3mA High state, I SOURCE = 3mA Low state, I SINK = 3mA High-impedance state; PWRGD, PHASEGD forced to 5V; TA = +25C Rising edge, 65mV typical hysteresis, controller disabled below this level VTHRM = VNTC = 1V VTHRM = VNTC = 1V 4.0 V3P3 0.4
4.5
40 0.993
60 1.03
A A/A
Measured at NTC with respect to THRM, VTHRM = 1V, falling edge; typical hysteresis = 100mV RON(VRHOT) Low state
-12
+12 8
mV
8
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = -40C to +105C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS VTIME - VILIM = 100mV VLIMIT VCSP_ - VCSN_ VTIME - VILIM = 500mV ILIM = VCC Current-Limit Threshold Voltage (Negative) Accuracy CSPAVG, CSP_, CSN_ Common-Mode Input Range Phase 2 Disable Threshold Droop Amplifier Offset Droop Amplifier Transconductance Gm(FB) Measured at CSP2 [VCSPAVG - (VCSN1 + VCSN2)/2] at IFB = 0 TA = +25C TA = 0C to +85C VLIMIT(NEG) VCSP_ - VCSN_-, nominally -125% of VLIMIT MIN 7 45 20 -5 0 3 -0.75 -1 1.173 TYP MAX 13 55 25 +5 2 VCC 0.4 +0.75 +1 1.224 mV V V mV mS mV UNITS
MAX17410
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive)
IFB/ [VCSPAVG - (VCSN1 + VCSN2)/2], VFB = VCSN- = 0.45V to 1.5V [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV
1.627
1.768 V
Power Monitor Output Voltage for Typical HFM Conditions
VPMON
V(OUTS, GNDS) = 1.200V, IPMON = 0A [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 500mV [VCSPAVG - (VCSN1 + VCSN2)/2] = 15mV, V(TIME, ILIM) = 225mV, I PMON = 0A V(CSN, GNDS) = 1.200V, V(TIME, ILIM) = 225mV, I PMON = 0A Measured at PMON with respect to unloaded voltage I PMON = 0 to 500A
0.734
0.796
Power Monitor Gain Referred to Output Voltage V(OUTS, GNDS) Power Monitor Gain Referred to [VCSPAVG - (VCSN1 + VCSN2)/2] Power Monitor Load Regulation Current Balance Amplifier Offset
APMON/VOUT APMON/VCS
1.375 104
1.452 123
V/V V/V
-6 -1.5 +1.5
V/A mV
(VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0
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9
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, VV3P3 = 3.3V, VDPRSLPVR = VDPRSTP = VGNDS = VPGND_ = 0, CSPAVG = CSP_ = CSN_ = OUTS = 1.0000V, RFB = 3.57k from FB to VPS, [D6-D0] = [0101000]; TA = -40C to +105C, unless otherwise noted.)
PARAMETER GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance Internal BST_ Switch On-Resistance LOGIC AND I/O Logic Input High Voltage Logic Input Low Voltage Low-Voltage Logic Input High Voltage Low-Voltage Logic Input Low Voltage VIH VIL VIHLV VILLV SHDN, PGDIN, DPRSLPVR SHDN, PGDIN, DPRSLPVR PSI, D0-D6, DPRSTP PSI, D0-D6, DPRSTP 0.67 0.33 2.3 1.0 V V V V R ON(DH_) R ON(DL_) R ON(BST_) BST_ - LX_ forced to 5V High state (pullup) Low state (pulldown) IBST_ = 10mA High state (pullup) Low state (pulldown) 2.5 2.0 2.0 0.7 20 SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DL_ and DH_ pins, with LX_ forced to GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times might be different due to MOSFET switching speeds.s
10
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 1.1500V, TA = +25C, unless otherwise specified.)
2-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 1.075V)
MAX17410 toc01
MAX17410
2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT(HFM) = 1.075V)
MAX17410 toc02
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 0.875V)
0.89 OUTPUT VOLTAGE (V) 0.88 0.87 0.86 0.85 0.84 0.83 SKIP MODE PWM MODE
MAX17410 toc03
1.15
100 7V 90 EFFICIENCY (%)
0.90
OUTPUT VOLTAGE (V)
1.10 80 12V 70 20V 60
1.05
1.00
0.95 0 10 20 LOAD CURRENT (A) 30 40
50 0.1 1 10 100 LOAD CURRENT (A)
0.82 0 5 10 LOAD CURRENT (A) 15 20
1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT(LFM) = 0.875V)
MAX17410 toc04
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17410 toc05
90 7V 80 EFFICIENCY (%) 70 60 50 40 30 0.1 1 10 20V 12V
400 350 SWITCHING FREQUENCY (kHz) 300 250 200 150 100 50 0 DPRSLPVR = VCC DPRSLPVR = GND 0 10 20 30 40 VOUT(LFM) = 0.875V VOUT(HFM) = 1.075V
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (VOUT(HFM) = 1.075V)
MAX17410 toc06
100
SUPPLY CURRENT (mA)
75 IIN 50 ICC + IDD 25 DPRSLPVR = GND PSI = VCC 0 9 12 15 18 21 24
SKIP MODE PWM MODE 100
50
0
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE AT SKIP MODE (VOUT(HFM) = 1.075V)
MAX17410 toc07
0.8125V OUTPUT-VOLTAGE DISTRIBUTION
MAX17410 toc08
Gm(FB) TRANSCONDUCTANCE DISTRIBUTION
35 SAMPLE PERCENTAGE (%) 30 25 20 15 10 5 0 +85C +25C SAMPLE SIZE = 100
MAX17410 toc09
10
70 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 +85C +25C SAMPLE SIZE = 100
40
SUPPLY CURRENT (mA)
ICC + IDD 1
0.1 IIN DPRSLPVR = VCC 6 9 12 15 18 21 24 INPUT VOLTAGE (V)
0.01
0 0.8115 0.8075 0.8085 0.8095 0.8105 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175
1180
1184
1188
1192
1196
1200
1204
1208
1212
1216
OUTPUT VOLTAGE (V)
TRANSCONDUCTANCE (S)
______________________________________________________________________________________
1220
11
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 1.1500V, TA = +25C, unless otherwise specified.)
CURRENT BALANCE vs. LOAD CURRENT
25
MAX17410 toc10
SOFT-START WAVEFORM (UP TO CLKEN)
0.5 0.4 0.3 V(CSP-CSN)1,2 (mV) 0.2
MAX17410 toc11
VOUT = 1.075V
5V 0 3.3V 0 1.075V C 0 0 0 200s/div A. SHDN, 5V/div B. CLKEN, 3.3V/div C. VOUT, 500mV/div D. ILX1, 10A/div E. ILX2, 10A/div IOUT = 0 D E A B
20 V(CSP-CSN)1,2 (mV)
15
VCSPN1 - VCSPN2
0.1 0
10
VCSP1 - VCSN1
-0.1 -0.2
5 VCSP2 - VCSN2 0 0 5 10 15 20 25 30 35 40 45 50 LOAD CURRENT (A)
-0.3 -0.4 -0.5
SOFT-START WAVEFORM (UP TO PWRGD)
MAX17410 toc12
SHUTDOWN WAVEFORM
MAX17410 toc13
LOAD-TRANSIENT RESPONSE (HFM MODE)
MAX17410 toc14
5V 0 3.3V 0 3.3V 0 3.3V 0 1.075V
A B C D E
5V 0 3.3V 0 3.3V 0 5V 0 1.075V
A B C D
47A 9A 1.075V
A
B 1V 25A 5A C
E 0 0 0 1ms/div A. SHDN, 10V/div B. CLKEN, 6.6V/div C. PWRGD, 10V/div D. PHASEGD, 10V/div F G 0 0 0 100s/div E. VOUT, 500mV/div F. ILX1, 10A/div G. ILX2, 10A/div IOUT = 0 A. SHDN, 10V/div B. PWRGD, 10V/div C. CLKEN, 6.6V/div D. DL1, 5V/div E. VOUT, 500mV/div F. ILX1, 10A/div G. ILX2, 10A/div
F G D 5A 20s/div A. IOUT = 9A-47A B. VOUT, 50mV/div C. ILX1, 10A/div D. ILX2, 10A/div
12
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 1.1500V, TA = +25C, unless otherwise specified.)
LOAD-TRANSIENT RESPONSE (LFM MODE)
MAX17410 toc15
MAX17410
ENTERING DEEPER SLEEP EXITING TO LFM (SLOW C4)
MAX17410 toc16
ENTERING DEEPER SLEEP EXITING TO NEAREST VID
MAX17410 toc17
20A 5A 0.875V
A
5V 0 5V 0 1.075V
A
5V 0 5V 0 1.075V
A
B
B
B
C 20A C 5A 0 20s/div A. IOUT = 5A-20A B. VOUT, 20mV/div C. ILX1, 10A/div PSI = GND DPRSLPVR = GND 100s/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div C. VOUT, 200mV/div IOUT = 3A E 0 40s/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div C. VOUT, 200mV/div IOUT = 3Av 0.65V 0 D 0.675V 0
C
D E
ENTERING DEEPER SLEEP EXITING TO LFM (FAST C4)
MAX17410 toc18
D0 12.5mV DYNAMIC VID CODE CHANGE
MAX17410 toc19
D3 10mV DYNAMIC VID CODE CHANGE
MAX17410 toc20
5V 0 5V 0 1.075V
A
5V A 0
5V 0 1.075V
A
B 1.075V 1.0625V B
B 0.975V
C 0.65V 0 0 100s/div A. DPRSTP, 5V/div D. ILX2, 10A/div B. DPRSLPVR, 10V/div E. ILX1, 10A/div IOUT = 3Av C. VOUT, 200mV/div D E
0
C
5A
C
0 100s/div A. VID0, 5V/div B. VOUT, 20mV/div C. ILX1, 10A/div D. ILX2, 10A/div
D
5A 100s/div A. D3, 5V/div B. VOUT, 50mV/div IOUT, = 10A C. ILX1, 10A/div D. ILX2, 10A/div
D
______________________________________________________________________________________
13
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 1.1500V, TA = +25C, unless otherwise specified.)
MAX17410 POWER MONITOR vs. LOAD CURRENT
MAX17410 toc21
MAX17410 POWER MONITOR vs. OUTPUT VOLTAGE
MAX17410 toc22
POWER MONITOR VID TRANSITION RESPONSE
MAX17410 toc23
1.5
VOUT = 1.075V
1.0
VIN = 12V IOUT = 20A
5V A 0 1.075V B 0.975V 0.35V 5A 5A D 100s/div A. D3, 5V/div B. VOUT, 50mV/div IOUT = 10A C. VPMON, 50mV/div D. ILX1, 10A/div E. ILX2, 10A/div C
0.8 POWER MONITOR (V)
POWER MONITOR (V)
1.0
0.6
0.4
0.5
0.2 DPRSLPVR = VCC DPRSLPVR = GND 0 0 5 10 15 20 25 30 35 40 LOAD CURRENT (A) 0 0 0.3 0.6 0.9 1.2 1.5 OUTPUT VOLTAGE (V)
OUTPUT UNDERVOLTAGE FAULT
MAX17410 toc24
OUTPUT OVERVOLTAGE WAVEFORM
MAX17410 toc25
BIAS SUPPLY REMOVAL (UVLO RESPONSE)
MAX17410 toc26
60A 0 0.875V 0 5V 0 3.3V 0 25A
A 1.075V B A C D 3.3V E 0 5V 0 100s/div A. IOUT, 100A/div B. VOUT, 500mV/div C. DL, 5V/div D. PWRGD, 3.3V/div E. ILX1, 10A/div A. VOUT, 500mV/div B. PWRGD, 3.3V/div 100s/div C. DL1, 5V/div DPRSLPVR = VCC B 0
5V A 1.075V B 0 3.3V 0 5V 0 0 40s/div A. 5V BIAS SUPPLY, 2V/div D. DL1, 5V/div B. VOUT, 500mV/div E. ILX1, 10A/div C. PWRGD, 3.3V/div IOUT = 5A
C D E
C
0
14
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Pin Description
PIN NAME FUNCTION Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if FB is in regulation, then PWRGD is high impedance. PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes high if FB is within the PWRGD threshold window. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and continues to be forced high impedance for an additional 20s after the transition is completed. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-ratecontrolled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. Power-State Indicator. This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to 1-phase forced-PWM mode. The controller returns to 2-phase forced-PWM mode when PSI is forced high. DPRSLPVR 1 1 0 0 PSI 0 1 0 1 Mode Very low current (1-phase skip) Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2)
MAX17410
1
PWRGD
2
PSI
The controller is in 2-phase skip mode during startup, but is in 2-phase forced-PWM mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is also in 2-phase skip mode while in boot mode, but is in 2-phase forced-PWM mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to VCC, then only phase 1 is active in the above modes. Power Monitor Output: V(PWR) = K PWR x V(OUTS, GNDS) x V(CSPAVG, CSN)/V(TIME, ILIM) where KPWR = 21.25 typical. If ILIM is externally connected to a 5V rail to enable the internal default/preset current-limit threshold, then the V(TIME, ILIM) value to be used in the above equation is 225mV. Do not use the power monitor in any configuration that would cause its output V(PMON) to exceed (VCC - 0.5V). PMON is pulled to ground when the MAX17410 is in shutdown. Resistive Input of Thermal Comparator. Connect a resistor to ground to set the VRHOT threshold. THRM and NTC have matched 50A current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. VRHOT is high impedance in shutdown. Thermistor Input of Thermal Comparator. Connect a standard thermistor to ground. THRM and NTC have matched 50A current sources, so the resistance value = the NTC resistance at the desired high temperature. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM.
3
PMON
4
THRM
5
VRHOT
6
NTC
______________________________________________________________________________________
15
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Pin Description (continued)
PIN NAME FUNCTION Open-Drain Phase-Good Output. Used to signal the system that one of the two phases either has a fault condition or is not matched with the other. Detection is done by identifying the need for a large (more than 40%) on-time difference between phases to achieve or move towards current balance. PHASEGD is low in shutdown, and when phase 2 is disabled by connecting CSP2 to VCC. PHASEGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions), and when phase 2 is disabled by the DPRSLPVR and/or PSI inputs. When phase 2 is reenabled, PHASEGD stays high impedance for 32 DH2 pulses, after which it monitors the difference between the on-times of the two phases. PHASEGD is also forced high impedance when VFB is below 0.5V. Power-Good Logic Input. Indicates the power status of other system rails and used for supply sequencing. Connect this pin to the 5V supply rail or float it if the feature is not needed. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT, and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGDIN input stays low. When PGDIN later goes high, the output is allowed to transition to the voltage set by the VID code, and CLKEN is allowed to go low. During normal operation, if PGDIN goes low, the controller immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in 2-phase skip mode at 1/8 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until the controller is turned off or power cycled, or until PGDIN goes high again. Feedback Voltage Input, and Output of the Voltage-Positioning Transconductance Amplifier. The voltage at the FB pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). Having sufficient ripple signal at FB that is in-phase with the sum of the inductor currents is essential for cycle-by-cycle stability. 9 FB Connect resistor RFB between FB and VPS to set the droop based on the voltage-positioning gain requirements: RFB = RDROOP/[RSENSE x Gm(FB)] where RDROOP is the desired voltage-positioning slope, Gm(FB) = 1.2mS typ, and RSENSE is the effective current-sense resistance that is used to provide the (CSPAVG, CSN_) current-sense voltage. If lossless sensing (inductor DCR sensing) is used, consider using a thermistor as part of the CSPAVG filter network to minimize the temperature dependence of the voltage-positioning slope. FB is high impedance in shutdown. 10 11 VPS SGND Internally Shorted to OUTS Through a 10 Resistance Internally Shorted SGND (Pin 11) to AGND (Pin 21) Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate. SLEW RATE = (12.5mV/s) x (71.5k /RTIME) where RTIME is between 35.7k and 178k . 12 TIME This "normal" slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is always 1/8 of normal. If DPRSLPVR and DPRSTP are both high, then the slew rate is reduced to 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_, CSN_) are precisely 1/10 the differential voltage V(TIME, ILIM) over a 0.1V to 0.5V range of V(TIME, ILIM). The valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of 22.5mV typ.
7
PHASEGD
8
PGDIN
13
ILIM
16
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Pin Description (continued)
PIN 14 NAME OUTS FUNCTION Output Remote Sense. Internally shorted to VPS through a 10 voltage feedback input to the power monitor. resistance. OUTS is also the
MAX17410
15
GNDS
Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS internally connects to a transconductance amplifier that fine tunes the output voltage-- compensating for voltage drops from the regulator ground to the load ground. Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the feedback remote-sense input (or between CCI and GND). CCI is internally forced low in shutdown. Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Positive Input of the Output Current-Sense Averaging Network. This input should be connected to the positive current-sense averaging network (see the standard 2-phase IMVP6+ application circuit of Figure 1) and is utilized for load line control and power monitoring (input of the transconductance amplifiers used for FB and PMON). Input Sense for On-Time Control. An internal resistor sets the switching frequency to 300kHz per phase. IN is high impedance in shutdown. Analog Ground Connect Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1F minimum. Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. Connect CSP2 to VCC to disable phase 2 and use the MAX17410 as a single-phase controller. In this configuration, connect LX2 to GND, connect BST2 to VDD, CSN2 to CSN1, and float DH2, DL2, CCI, and PHASEGD. Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of the output current-sensing resistor, or to the filtering capacitor if the DC resistance of the output inductor is used for current sensing. This pin is utilized for current limit and current balance only. No Connection. Not internally connected. Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-side gate driver. An internal switch between VDD and BST2 charges the BST2 - LX2 flying capacitor while the low-side MOSFET is on (DL2 pulled high). Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2's zero-crossing comparator. Power Ground. PGND2 is the internal lower supply rail for the DL2 low-side gate driver. Phase 2 Low-Side Gate-Driver Output. DL2 swings from PGND2 to VDD. DL2 is forced low in shutdown. DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor current zero crossing. Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge the BST_ - LX_ flying capacitor during the times the respective DL_ are high. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1F or greater ceramic capacitor.
16
CCI
17
CSN2
18
CSN1
19
CSPAVG
20 21 22
IN GND VCC
23
CSP2
24 25 26 27 28 29
CSP1 N.C. BST2 DH2 LX2 PGND2
30
DL2
31
VDD
______________________________________________________________________________________
17
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Pin Description (continued)
PIN NAME FUNCTION Phase 1 Low-Side Gate-Driver Output. DL1 swings from PGND1 to VDD. DL1 is forced low in shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor current zero crossing. Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver. Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1's zero-crossing comparator. Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-side gate driver. An internal switch between VDD and BST1 charges the BST1 - LX1 flying capacitor, while the low-side MOSFET is on (DL1 pulled high). Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0-D6 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D0-D6 (see Table 4). Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into the 1A (max at TA = +25C) shutdown state. During startup, the output voltage is ramped up at 1/8 the slew rate set by the TIME resistor to the boot voltage. During the transition from normal operation to shutdown, the output voltage is ramped down at 1/8 the slew rate set by the TIME resistor. Forcing SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and thermal shutdown, clears the fault latches, disables transient phase overlap, disables soar suppression, and turns off the internal BST_-to-VDD switches. However, internal diodes still exist between BST_ and VDD in this state. 3.3V Logic Input. Indicates power usage and sets the operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1phase automatic pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. During this blanking period, the overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.8V threshold. DPRSLPVR 45 DPRSLPVR 1 1 0 0 PSI 0 1 0 1 Mode Very low current (1-phase skip) Low current (approx 3A) (1-phase skip) Intermediate power potential (1-phase PWM) Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at CSP2)
32
DL1
33 34 35 36
PGND1 LX1 DH1 BST1
37-43
D0-D6
44
SHDN
The controller is in 2-phase skip mode during startup, but is in 2-phase forced-PWM mode during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is in 2-phase skip mode while in boot mode, but is in 2-phase forced-PWM mode during the transition from boot mode to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled by connecting CSP2 to VCC, then only phase 1 is active in the above modes.
18
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Pin Description (continued)
PIN NAME FUNCTION Low-Voltage Logic Input Signal. This is usually the logical complement of the DPRSLPVR signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could temporarily be simultaneously high. If this happens, the MAX17410 reduces the slew rate to 1/4 the normal (RTIME-based) slew rate for the duration of this condition. The slew rate returns to normal when this condition is exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs. skip and number of active phases). 46 DPRSTP DPRSLPVR 0 0 1 1 DPRSTP 0 1 0 1 Functionality Normal slew rate, 1- or 2-phase forced-PWM mode (DPRSLPVR low DPRSTP is ignored) Normal slew rate, 1- or 2-phase forced-PWM mode (DPRSLPVR low DPRSTP is ignored) Normal slew rate, 1-phase automatic pulse-skipping mode Slew rate reduced to 1/4th of normal, 1-phase automatic pulse-skipping mode
MAX17410
47
CLKEN
Clock Enable CMOS Push-Pull Logic Output Powered by V3P3. This inverted logic output indicates when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an additional 20s after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. 3.3V Supply Input for the CLKEN CMOS Push-Pull Logic Output. Connect to the 3.0V to 3.6V system supply voltage. Exposed Backplate (Paddle) of Package. Internally connected to analog ground. Connect to the ground plane through a thermally enhanced via.
48 --
V3P3 EP
______________________________________________________________________________________
19
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
37 38 39 40 41 42 43 44 45 47 3.3V 10k R4 10k R5 10k 1 5 7 4.99k 4 PWRGD VRHOT PHASEGD THRM 48 D0 D1 D2 D3 D4 D5 D6 SHDN BST1 DPRSLPVR CLKEN LX1 V3P3 DL1 PGND1 CSP1 PGDIN CSN1 CSN2 CCI MAX17410 NTC CSPAVG 46 DPRSTP 2 PSI OPEN 10k C8 0.1F AGND 3 N.C. 19 25 0.1F 23 R13 0 2k C8 0.22F NLO NHI 3.32k 1 PWR OPEN COUT 1.5k 10k NTC = 3380 DH1 VCC 22 R1 10 C1 1F AGND INPUT 7V TO 24V C2 1F 5V BIAS INPUT
VID INPUTS
GND VDD IN
21 31 20 36 35 34 32 33 24 8 18 17 16
ON OFF (VRON)
R9 0 NHI
CIN PWR L1 0.36H 0.82m
C4 0.22F NLO
COUT
D1
3.32k OPEN
1
PWR COUT = 4 x 330F/4.5m + 32 x 10F MLCC
PWR 0.1F
0 1000pF
0.1F 2k 0.47F CORE OUTPUT OPEN
AGND 100k NTC = 4700
6
AGND
CSP2 PMON BST2 DH2 13 LX2 DL2
26 27 28 30 29 14
ILIM
L2 D1 R20 10 C9 1000pF AGND R22 25 VCC_SENSE REMOTE-SENSE INPUTS VSS_SENSE R23 25 CATCH RESISTORS REQUIRED WHEN CPU PWR NOT POPULATED
61.9k
10k 12 TIME 11 SGND OPEN PGND2 OUTS
PWR
AGND
10
VPS GNDS 15
R21 10
OPEN
4.02k 9 FB
C10 1000pF AGND REMOTE-SENSE FILTERS
Figure 1. Standard 2-Phase IMVP6+ Application Circuit
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
MAX17410 BST2 NTC THRM VRHOT DH2 SECONDARY PHASE DRIVERS LX2 DL2 PGND2 CSP2 CSN2 BLANK 1X 0.1X EN2 Q TRIG CURRENTBALANCE FAULT 5ms STARTUP DELAY CCI CSN2 CSP2 CSP1 FB CSN1 IN MAIN PHASE DRIVERS PHASEGD
CSP1 CSN1 VCC REF (2.0V) GND SGND 2.5 REF
PHASE 2 ON-TIME ONE-SHOT 1X 0.1X MINIMUM OFF-TIME Q TRIG
ONE SHOT PHASE 1 ON-TIME ONE-SHOT Q TRIG
Gm(CCI)
FB DPRSLPVR R-TO-I CONVERTER DAC
Gm(CCI)
ILIM TIME D0-D6 DPRSTP SHDN
R Q S
BST1 DH1 LX1
PGND1 FAULT REF Gm(CCV) SKIP TARGET Q T Q LX1 1mV
S Q R VDD
DL1
TARGET - 300mV FB
TARGET + 200mV
PGND1 PWRGD 5ms STARTUP DELAY V3P3
CSN1 CSN2 CSPAVG GNDS Gm(FB)
VCC EN2 SKIP BLANK CSPAVG, CSN1, CSN2 10 OUTS GNDS VPS
60s STARTUP DELAY
CLKEN
PHASE CONTROL
POWER MONITOR
PMON
PGDIN DRPSLPVR
PSI
OUTS
Figure 2. Functional Diagram
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Table 1. Component Selection for Standard Applications
DESIGN PARAMETERS Circuit Input Voltage Range Maximum Load Current Transient Load Current Load Line Inductance (L) High-Side MOSFET (NH) Low-Side MOSFET (NL) IMVP6+ SV Figure 1 7V to 20V 44A (34A) 35A (10A/s) -2.1mV/A NEC/Tokin MPC1055LR36 0.36H, 32A, 0.8m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 2x Si4642DY 3.9m /4.7m (typ/max) 3x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR 28x 10F, 6V ceramic (0805) 4x 10F, 25V ceramic (1210) 10k 61.9k 4.02k 2k 1.50k open 10k NTC B = 3380 TDK NTCG163JH103F 0.47F, 6V ceramic (0805) IMVP6+ LV Figure 1 7V to 20V 23A (19A) 18A (10A/s) -4mV/A NEC/Tokin MPC1055LR36 0.36H, 32A, 0.8m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 2x Si4642DY 3.9m /4.7m (typ/max) 3x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR 28x 10F, 6V ceramic (0805) 4x 10F, 25V ceramic (1210) 6.19k 64.9k 7.68k 2k 1.50k open 10k NTC B = 3380 TDK NTCG163JH103F 0.47F, 6V ceramic (0805)
Output Capacitors (COUT) Input Capacitors (CIN) TIME-ILIM Resistance (R1) ILIM-GND Resistance (R2) FB Resistance (RFB) LX-CSP Resistance (R5) CSP-CSN Series Resistance (R6) Parallel NTC Resistance (R7) DCR Sense NTC (NTC1) DCR Sense Capacitance (CSENSE)
Table 2. Component Suppliers
MANUFACTURER AVX Corporation BI Technologies Central Semiconductor Corp. Fairchild Semiconductor International Rectifier KEMET Corp. NEC/TOKIN America, Inc. Panasonic Corp. WEBSITE www.avxcorp.com www.bitechnologies.com www.centralsemi.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokin.com www.panasonic.com MANUFACTURER Pulse Engineering Renesas Technology Corp. SANYO Electric Co., Ltd. Sumida Corp. Taiyo Yuden TDK Corp. TOKO America, Inc. Vishay/Siliconix WEBSITE www.pulseeng.com www.renesas.com www.sanyodevice.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.vishay.com
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
MAX17410 Detailed Description
Free-Running, Constant On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor's ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to the input voltage, and directly proportional to the output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. The controller maintains 180 out-ofphase operation by alternately triggering the main and secondary phases after the error comparator drops below the output-voltage set point.
+5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator. The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is:
IBIAS = I CC + fSW Q G(LOW) + Q G(HIGH)
MAX17410
(
)
Dual 180 Out-of-Phase Operation
The two phases in the MAX17410 operate 180 out-ofphase to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count--reducing cost, board space, and component power requirements--making the MAX17410 ideal for high-power, cost-sensitive applications. Typically, switching regulators provide power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high RMS ripple current can lower efficiency due to I2R power loss associated with the input capacitor's effective series resistance (ESR). Therefore, the system typically requires several lowESR input capacitors in parallel to minimize input voltage ripple, to reduce ESR-related power losses, and to meet the necessary RMS ripple current rating. With the MAX17410, the controller shares the current between two phases that operate 180 out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively halved, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). Therefore, the same performance may be achieved with fewer or less expensive input capacitors.
where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet's total gatecharge specification limits at VGS = 5V. VIN and VDD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Switching Frequency
IN (Pin 20) Open-Circuit Protection The MAX17410 input sense (IN) is used to adjust the ontime. An internal resistor sets the switching frequency to 300kHz per phase. IN is high impedance in shutdown. On-Time One-Shot The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET's on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB):
t ( V + 0.075V ) t ON(MAIN) = SW FB VIN where the switching period (tSW = 1/fSW) is set to 3.3s internally, and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch.
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
The one-shot for the secondary phase varies the ontime in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB. The resulting compensation current and voltage are determined by the following equations: I CCI = G m ( VCSP1 - VCSN1) - G m ( VCSP2 - VCSP2 ) VCCI = VFB + I CCIZ CCI where ZCCI is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (VCCI) to set the secondary high-side MOSFET's ontime. When the main and secondary current-sense signals become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced:
V + 0.075V t ON(SEC) = t SW CCI VIN V + 0.075V I CCIZ CCI 7 = t SW FB + t SW V VIN IN
dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: fSW = t ON ( VIN + VDIS - VCHG )
( VOUT + VDIS )
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as defined in the Electrical Characteristics table.
Current Sense
The output current of each phase is sensed. Low offset amplifiers are used for current balance, voltagepositioning gain, and current limit. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage drooperror budget and power monitor. This current-sense method uses an RC filtering network to extract the current information from the output inductor (see Figure 3). The resistive divider used should provide a current-sense resistance (RCS) low enough to meet the current-limit requirements, and the time constant of the RC network should match the inductor's time constant (L/RCS): R2 R CS = R R1 + R2 DCR and: R CS = L 1 1 R1 + R2 C EQ
= (Main On-time) + ( Secondary Current Balance Correction) t
This algorithm results in a nearly constant switching frequency and balanced inductor currents despite the lack of a fixed-frequency clock generator. The constant switching frequency allows the inductor ripple-current operating point to remain relatively constant, resulting in easy design methodology and predictable output voltage ripple. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PCB copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forcedPWM operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH rising
where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. To minimize the current-sense error due to the current-sense inputs' bias current (ICSP_ and ICSN_), choose R1 || R2 to be less than 2k and use the above equation to
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
determine the sense capacitance (C EQ ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section for detailed information. When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 3). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method, the RC filter's time constant should match the L/R time constant formed by the current-sense resistor's parasitic inductance: L ESL = C EQR1 R SENSE where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, C EQ and R1 are the time-constant matching components.
MAX17410
INPUT (VIN) DH_ LX_ MAX17410 DL_ PGND CSP_ CSN_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH_ LX_ MAX17410 DL_ PGND CSP_ CSN_ B) LOSSLESS INDUCTOR SENSING FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR. DL R1 R2 CEQ COUT L RCS = C x EQ 1 1 [ R1 + R2 ] NH CIN L INDUCTOR RDCR RCS = NL R2 RDCR R1 + R2 DL R1 CEQ COUT NH CIN L SENSE RESISTOR LESL RSENSE L CEQR1 = ESL RSENSE
NL
Figure 3. Current-Sense Methods
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Current Balance
The MAX17410 integrates the difference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the currentsense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side MOSFETs. With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: IOS(IBAL) = ILMAIN - ILSEC = VOS(IBAL) R CS The negative current-limit threshold (forced-PWM mode only) is nominally -125% of the corresponding valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse--DL turns off, and DH turns on--allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP_, CSN_).
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop) The MAX17410 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier's input is generated by summing the current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor's DCR. The amplifier's output connects directly to the regulator's voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltage-positioning gain:
VOUT = VTARGET - R FBIFB where the target voltage (VTARGET) is defined in the Nominal Output Voltage Selection section, and the FB amplifier's output current (IFB) is determined by the average value of the current-sense voltages: IFB = G m(FB) x VCSPAVG-CSN where V CS = V CSPAVG-CSN is the average currentsense voltage between the CSPAVG and the CSN_ pins, and Gm(FB) is typically 1.2mS as defined in the Electrical Characteristics table.
where R CS is the effective sense resistance and VOS(IBAL) is the current-balance offset specification in the Electrical Characteristics table. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency.
Current Limit The current-limit circuit employs a unique "valley" current-sensing algorithm that uses current-sense resistors between the current-sense inputs (CSP_ to CSN_) as the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase. Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. The positive valley current-limit threshold voltage at CSP to CSN equals precisely 1/10th the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV (typ).
Differential Remote Sense The MAX17410 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor's power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (R FB ), and ground-sense (GNDS) input directly to the processor's remote-sense outputs as shown in Figure 1.
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Integrator Amplifier An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by 100mV (typ). The differential input voltage range is at least 60mV total, including DC offset and AC ripple. The MAX17410 disables the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (DPRSLPVR = high). The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
Nominal Output Voltage Selection
The nominal no-load output voltage (V TARGET ) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, the MAX17410 slews the target voltage from ground to the preset boot voltage.
MAX17410
Transient Overlap Operation
When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180 out-ofphase when a transient occurs actually respond slower than an equivalent single-phase controller. To provide fast transient response, the MAX17410 supports a phase overlap mode that allows the dual regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. After either high-side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs during the next ontime cycle. This maximizes the total inductor current slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum off-time expires. After the phase overlap mode ends, the controller automatically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends.
DAC Inputs (D0-D6) The digital-to-analog converter (DAC) programs the output voltage using the D0-D6 inputs. D0-D6 are low-voltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0-D6 unconnected. Changing D0-D6 initiates a transition to a new output voltage level. Change D0-D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the IMVP6/IMVP6+ (Table 4) specifications. Suspend Mode When the processor enters low-power deeper sleep mode, the IMVP6 CPU sets the VID DAC code to a lower output voltage and drives DPRSLPVR high. The MAX17410 responds by slewing the internal target voltage to the new DAC code, switching to single-phase operation, and letting the output voltage gradually drift down to the deeper sleep voltage. During the transition, the MAX17410 blanks both the upper and lower PWRGD and CLKEN thresholds until 20s after the internal target reaches the deeper sleep voltage. Once the 20s timer expires, the MAX17410 re-enables the lower PWRGD and CLKEN threshold, but keeps the upper threshold blanked. PHASEGD remains blanked high impedance while DPRSLPVR is high.
Table 3. Operating Mode Truth Table
INPUTS SHDN GND DPRSTP X DPRSLPVR X PSI X PHASE OPERATION* DISABLED Multiphase Skipping 1/8 RTIME Slew Rate OPERATING MODE Low-Power Shutdown Mode. DL1 and DL2 forced low, and the controller is disabled. The supply current drops to 1A (max). Startup/Boot. When SHDN is pulled high, the MAX17410 begins the startup sequence and ramps the output voltage up to the boot voltage. See Figure 9.
Rising
X
X
X
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Table 3. Operating Mode Truth Table (continued)
INPUTS SHDN DPRSTP DPRSLPVR PSI PHASE OPERATION* Multiphase Forced-PWM Nominal RTIME Slew Rate 1-Phase Forced-PWM Nominal RTIME Slew Rate OPERATING MODE
High
X
Low
High
Full Power. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). Intermediate Power. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). When PSI is pulled low, the MAX17410 immediately disables phase 2--DH2, and DL2 pulled low. Deeper Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). When DPRSLPVR is pulled high, the MAX17410 immediately enters 1-phase pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low. Deeper Sleep Slow Exit Mode. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). When DPRSTP is pulled high while DPRSLPVR is already high, the MAX17410 remains in 1-phase pulse-skipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low. Shutdown. When SHDN is pulled low, the MAX17410 immediately pulls PWRGD and PHASEGD low, CLKEN becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to ground. Once the output reaches 0V, the controller enters the low-power shutdown state. See Figure 9. Fault Mode. The fault latch has been set by the MAX17410 UVP or thermal-shutdown protection, or by the OVP protection. The controller will remain in FAULT mode until VCC power is cycled or SHDN toggled.
High
X
Low
Low
High
Low
High
X
1-Phase PulseSkipping Nominal RTIME Slew Rate
High
High
High
X
1-Phase PulseSkipping 1/4th RTIME Slew Rate
Falling
X
X
X
Multiphase Forced-PWM 1/8th RTIME Slew Rate
High
X
X
X
DISABLED
*Multiphase Operation = All enabled phases active. X = Don't care.
Table 4. IMVP6+ Output Voltage VID DAC Codes
D6 0 0 0 0 0 0 D5 0 0 0 0 0 0 D4 0 0 0 0 0 0 D3 0 0 0 0 0 0 D2 0 0 0 0 1 1 D1 0 0 1 1 0 0 D0 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 D6 0 0 0 0 0 0 D5 0 0 0 0 0 0 D4 0 0 0 0 0 0 D3 0 0 1 1 1 1 D2 1 1 0 0 0 0 D1 1 1 0 0 1 1 D0 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Table 4. IMVP6+ Output Voltage VID DAC Codes (continued)
D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT VOLTAGE (V) 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 D2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875
MAX17410
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Table 4. IMVP6+ Output Voltage VID DAC Codes (continued)
D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 D2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT VOLTAGE (V) 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0 0 0 0 0 0 0 0
Output-Voltage Transition Timing
The MAX17410 performs mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output voltage transition, the MAX17410 blanks both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20s after the slewrate controller reaches the target output voltage, but the upper PWRGD threshold is enabled only if the controller remains in forced-PWM operation. If the controller enters pulse-skipping operation, the upper PWRGD threshold remains blanked. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition may be completed within the maximum allotted time. The MAX17410 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal
30
capacitor and current-source programmed by RTIME to transition the output voltage. The total transition time depends on R TIME , the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by: t TRAN = VNEW - VOLD (dVTARGET / dt )
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See the time slew-rate accuracy in the Electrical Characteristics table for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8th. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an output voltage transition is:
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
IL C OUT x (dVTARGET / dt ) TOTAL remains blanked high impedance until 20s after the output voltage reaches the internal target. Once this time expires, PWRGD monitors only the lower threshold. Fast C4E Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the MAX17410 quickly slews (50mV/s min regardless of RTIME setting) the internal target voltage to the DAC code provided by the processor as long as the output voltage is above the new target. The controller remains in skip mode until the output voltage equals the internal target. Once the internal target reaches the output voltage, phase 2 is enabled. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 4.
MAX17410
where dVTARGET/dt is the required slew rate, COUT is the total output capacitance, and TOTAL is the number of active phases.
Deeper Sleep Transitions When DPRSLPVR goes high, the MAX17410 immediately disables phase 2 (DH2 and DL2 forced low), blanks PHASEGD high impedance, and enters pulse-skipping operation (see Figures 4 and 5). If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target still ramps as before, and PWRGD
ACTUAL VOUT CPU CORE VOLTAGE INTERNAL TARGET VID (D0-D6) DPRSLPVR DPRSTP PSI INTERNAL PWM CONTROL DH1 DH2 PWRGD CLKEN PHASEGD OVP tBLANK 20s TYP BLANK HIGH-Z BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK HIGH THRESHOLD ONLY BLANK HI-Z (1-PHASE OPERATION) SET TO 1.75V MIN TRACKS INTERNAL TARGET tBLANK 20s TYP BLANK HI-Z BLANK LOW DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) NO PULSES: VOUT > VTARGET FORCED PWM DEEPER SLEEP VID
Figure 4. C4E (C4 Early Exit) Transition
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Standard C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep voltage, the MAX17410 immediately activates all enabled phases and ramps the output voltage to the LFM DAC code provided by the processor at the slew rate set by RTIME. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 5.
ACTIVE VID CPU CORE VOLTAGE ACTUAL VOUT INTERNAL TARGET DEEPER SLEEP VID LFM VID LFM VID DPRSLP VID
VID (D0--D6) DPRSLPVR DPRSTP PSI INTERNAL PWM CONTROL DH1 DH2 PWRGD CLKEN PHASEGD OVP SET TO 1.75V MIN BLANK HIGH-Z BLANK LOW
DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) NO PULSES: VOUT > VTARGET 1-PHASE FORCED PWM
BLANK HIGH THRESHOLD ONLY BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z (1-PHASE OPERATION)
BLANK HIGH-Z BLANK LOW
TRACKS INTERNAL TARGET
tBLANK 20s TYP
tBLANK 20s TYP
Figure 5. Standard C4 Transition
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Slow C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR high, DPRSTP pulled high) while the output voltage is regulating to the deeper sleep voltage, the MAX17410 remains in 1-phase skip mode and ramps the output voltage to the LFM DAC code provided by the processor at 1/4 the slew rate set by RTIME. The controller blanks PWRGD, PHASEGD, and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 6.
MAX17410
ACTIVE VID CPU CORE VOLTAGE INTERNAL TARGET VID (D0-D6) DPRSLPVR DPRSTP PSI INTERNAL PWM CONTROL DH1 DH2 PWRGD CLKEN PHASEGD OVP SET TO 1.75V MIN tBLANK 20s TYP BLANK HIGH-Z BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z (1-PHASE OPERATION) DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW) NO PULSES: VOUT > VTARGET DEEPER SLEEP VID ACTUAL VOUT
SLOW SLEW RATE LFM VID DPRSLP VID LFM VID SLOW SLEW RATE
1-PHASE FORCED PWM
BLANK HIGH-Z BLANK LOW
TRACKS INTERNAL TARGET tBLANK 20s TYP
Figure 6. Slow C4 Transition
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
PSI Transitions When PSI is pulled low, the MAX17410 immediately disables phase 2 (DH2 and DL2 forced low), blanks PHASEGD high impedance, and enters single-phase PWM operation (see Figure 7). When PSI is pulled high, the MAX17410 enables phase 2. PHASEGD is blanked high impedance for 32 switching cycles on DH2, allowing sufficient time/cycles for phase 1 and 2 to achieve current balance. In a typical IMVP-6 application, the VID is reduced by 1 LSB (12.5mV) when PSI is pulled low, and increased by 1 LSB when PSI is pulled high.
constantly be the complement of the high-side gatedrive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. PSI determines how many phases are active when operating in forced-PWM mode (DPRSLPVR = low). When PSI is pulled low, the main phase remains active but the secondary phase is disabled (DH2 and DL2 forced low).
MAX17410
Forced-PWM Operation (Normal Mode)
During soft-start, soft-shutdown, and normal operation-- when the CPU is actively running (DPRSLPVR = low, Table 5)--the MAX17410 operates with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to
CPU FREQ
CPU LOAD
VID (D0-D6)
CPU CORE VOLTAGE
PSI INTERNAL PWM CONTROL 2-PHASE PWM 1-PHASE PWM 2-PHASE PWM
PWRGD CLKEN PHASEGD
BLANK HIGH-Z BLANK LOW BLANK HIGH-Z tBLANK 20s TYP
BLANK HIGH-Z BLANK LOW
tBLANK 20s TYP 32 DH2 SWITCHING CYCLES
Figure 7. PSI Transition
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Light-Load Pulse-Skipping Operation (Deeper Sleep)
When DPRSLPVR is pulled high, the MAX17410 operates with a single-phase pulse-skipping mode. The pulse-skipping mode enables the driver's zero-crossing comparator, so the controller pulls DL1 low when its current-sense inputs detect "zero" inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light load conditions to avoid overcharging the output. When pulse-skipping, the controller blanks the upper PWRGD and CLKEN thresholds, and also blanks PHASEGD high impedance. Upon entering pulseskipping operation, the controller temporarily sets the OVP threshold to 1.80V, preventing false OVP faults when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. The MAX17410 automatically uses forced-PWM operation during soft-start and soft-shutdown, regardless of the DPRSLPVR and PSI configuration. input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: t V V -V ILOAD(SKIP) = TOTAL SW OUT IN OUT L VIN where TOTAL is the number of active phases. The switching waveforms may appear noisy and asynchronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs between PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels.
MAX17410
Automatic Pulse-Skipping Switchover In skip mode (DPRSLPVR = high), an inherent automatic switchover to PFM takes place at light loads (Figure 8). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics table), the comparator forces DL low (Figure 2). This mechanism causes the threshold between pulse-skipping PFM and non-skipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 8). For a battery
i VIN - VOUT = t L INDUCTOR CURRENT IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Power-Up Sequence (POR, UVLO)
The MAX17410 is enabled when SHDN is driven high (Figure 9). The reference powers up first. Once the reference exceeds its undervoltage lockout threshold, the internal analog blocks are turned on and masked by a 150s one-shot delay. The PWM controller then begins switching. Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC undervoltage lockout (UVLO) circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, V CC above 4.25V and SHDN driven high. With the reference in regulation, the controller ramps the output voltage to the boot voltage (1.2V) at 1/8th the slew rate set by RTIME: t TRAN(START) = 8VBOOT (dVTARGET / dt ) current limit, so full output current is available immediately. CLKEN is pulled low approximately 60s after the MAX17410 reaches the boot voltage. At the same time, the MAX17410 slews the output to the voltage set at the VID inputs at the programmed slew rate. PWRGD and PHASEGD becomes high impedance approximately 5ms after CLKEN is pulled low. The MAX17410 automatically uses forced-PWM operation during soft-start and soft-shutdown, regardless of the DPRSLPVR and PSI configuration. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output.
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. The soft-start circuitry does not use a variable
VCC SHDN
VID (D0-D6) SOFT-START = 1/8 SLEW RATE SET BY RTIME VCORE INTERNAL PWM CONTROL PHASEGD CLKEN PWRGD
INVALID CODE
INVALID CODE SOFT-SHUTDOWN = 1/8 SLEW RATE SET BY RTIME
SKIP
FORCED-PWM
FORCED-PWM
tBLANK 60s TYP
tBLANK 5ms TYP
tBLANK 20s TYP
tBLANK 20s TYP
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Shutdown
When SHDN goes low, the MAX17410 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/8th the slew rate set by RTIME: 8VOUT t TRAN(SHDN) = (dVTARGET / dt ) where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17410 shuts down completely--the drivers are disabled (DL1 and DL2 driven high), the reference turns off, and the supply current drops below 1A. When a fault condition--output UVLO or thermal shutdown--activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V.
Phase Fault (PHASEGD)
The MAX17410 includes a phase fault output that signals the system that one of the two phases either has a fault condition or is not matched with the other. Detection is done by identifying the need for a large ontime difference between phases to achieve or move towards current balance. PHASEGD is forced low when VCCI is below (0.6 x VFB) or above (1.4 x VFB). PHASEGD is high impedance when the controller operates in one-phase mode (DPRSLPVR high, or PSI low and DPRSLPVR low). On exit to two-phase mode, PHASEGD is forced high impedance for 32 switching cycles on DH2. PHASEGD is low in shutdown. PHASEGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions).
MAX17410
Temperature Comparator (VRHOT)
VRHOT is an open-drain output of the internal comparator. VRHOT is pulled low when the voltage at NTC goes below the voltage at THRM. VRHOT is high impedance in shutdown.
Fault Protection (Latched)
Output Overvoltage Protection The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17410 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV, regardless of the operating state. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold tracks the VID DAC voltage.
When the OVP circuit detects an overvoltage fault while in multiphase mode (DPRSLPVR = low, PSI = high), the MAX17410 immediately forces DL1 and DL2 high, pulls DH1 and DH2 low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When an overvoltage fault occurs while in one-phase operation (DPRSLPVR = high, or PSI = low), the MAX17410 immediately forces DL1 high, pulls DH1 low. DL2 and DH2 remain low as phase two was disabled. DL2 is forced high only when the output falls below the UV threshold. Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section).
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Power Monitor (PMON)
The MAX17410 include a single-quadrant multiplier used to determine the actual output power based on the inductor current (the differential CS input) and output voltage (CSN to GNDS). The buffered output of this multiplier is connected to PWR and provides a voltage relative to the output power dissipation: V(PMON) = Kpwr x V(OUTS, GNDS) x V(CSPAVG, CSN) / V(TIME, ILIM) where VCSP - VCSN = ILOAD x RSENSE, and the power monitor scale factor (Kpwr) is typically 21.25. If ILIM is externally connected to a 5V rail to enable the internal default/preset current-limit threshold, then the V(TIME, ILIM) value to be used in the above equation is 225mV. Do not use the power monitor in any configuration that would cause its output V(PMON) to exceed (VCC - 0.5V). PMON is pulled to ground when the MAX17410 is in shutdown. The power monitor allows the system to accurately monitor the CPU's power dissipation and quickly predict if the system is about to overheat before the significantly slower temperature sensor signals an overtemperature alert.
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
Output Undervoltage Protection The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX17410 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to zero, it forces DL1 and DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller.
UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section). There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17410 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.25 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require rising LX edges do not pull up the low-side MOSFETs' gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS C ISS Typically, adding a 4700pF between DL and power ground (C NL in Figure 10), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.
(RBST)* INPUT (VIN) CBST NH L
Thermal-Fault Protection The MAX17410 features a thermal fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latch and activates the softshutdown sequence. Once the controller ramps down to zero, it forces DL1 and DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section). No-Fault Test Mode The latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a "no-fault" test mode is provided to disable the fault protection--overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN.
BST_
DH_ LX_
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST_, while the DL_ synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency.
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VDD
CBYP
DL_ (CNL)* PGND
NL
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 10. Gate-Drive Circuit
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R BST in Figure 10). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. * Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
MAX17410
*
Multiphase Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VOUT VIN - VOUT L = TOTAL fSWILOAD(MAX)LIR VIN where TOTAL is the total number of phases. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ILOAD(MAX) LIR IPEAK = 1+ 2 TOTAL
For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: I ILOAD(PHASE) = LOAD TOTAL where TOTAL is the total number of active phases.
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the worst-case output sag voltage may be determined by:
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
L ILOAD(MAX) +t M VIN OFF(MIN) VSAG = ( VIN - 2VOUT ) t SW 2C OUT VOUT - 2t OFF(MIN) VIN ILOAD(MAX) VOUT t SW +t + 2C OUT VIN OFF(MIN)
(
)
2 VOUT t SW
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR
In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output-ripple voltage. The output-ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-of-phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For multiphase operation, the maximum ESR to meet ripple requirements is: VINfSWL R ESR V VIN - TOTAL VOUT ) VOUT RIPPLE ( where TOTAL is the total number of active phases and fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
MAX17410
( ILOAD(MAX) ) 2 L
2 TOTAL C OUT VOUT
where TOTAL is the total number of active phases.
Setting the Current Limit
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ILOAD(MAX) LIR ILIMIT(LOW) > 1- 2 TOTAL where TOTAL is the total number of active phases, and ILIMIT(LOW) equals the minimum current-limit threshold voltage divided by the current-sense resistor (RSENSE). For the 22.5mV default setting, the minimum currentlimit threshold is 19.5mV.
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR SW where: fESR = and: R EFF = R ESR + R DROOP + R PCB where COUT is the total output capacitance, RESR is the total equivalent-series-resistance, RDROOP is the voltagepositioning gain, and RPCB is the parasitic board resistance between the output capacitors and sense resistors. 1 2R EFF C OUT
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
(RESR + RPCB ) I
VSTEP
LOAD(MAX)
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in wide-spread use at the time of publication have typical ESR zero frequencies below 50kHz. In the standard application circuit, the ESR needed to support a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5m. Four 330F/2.5V Panasonic SP (type SX) capacitors in parallel provide 1.5m (max) ESR. With a 2m droop and 0.5m PCB resistance, the typical combined ESR results in a zero at 30kHz. Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PCB resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Doublepulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX17410
ILOAD IRMS = TOTAL VOUT ( VIN - TOTAL VOUT ) TOTAL VIN
where TOTAL is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with V IN = 2TOTALVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/TOTAL. For most applications, non-tantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Driver section).
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, while the Quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/TOTAL per phase, the IRMS requirements may be determined by the following equation:
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: V I PD (N H Resistive) = OUT LOAD R DS(ON) VIN TOTAL where TOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: VIN(MAX)ILOADfSW Q G(SW) PD (N H Switching) = I TOTAL GATE + C OSS VIN 2 fSW 2
2
The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "over design" the circuit to tolerate: I ILOAD = TOTAL I VALLEY(MAX) + INDUCTOR 2 ILOAD(MAX)LIR = TOTALI VALLEY(MAX) + 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current per phase during the dead times. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: C BST = N x Q GATE 200mV
where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A, typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
V ILOAD 2 OUT PD (N L Resistive) = 1- R DS(ON) VIN(MAX) TOTAL
42
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: C BST = 2 x 24nC = 0.24F 200mV
Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (CCCI) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R CCI = 200k) improves transient response by increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator's output works well. Connecting the compensation network to the output (VOUT) allows the controller to feed-forward the output voltage signal, especially during transients. To reduce noise pick-up in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than VOUT. in the Electrical Characteristics table. The controller uses the CSPAVG pin to get the average inductor current from the positive current-sense averaging network. When the inductors' DCR is used as the current-sense element (RSENSE = RDCR), the current-sense inputs should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
MAX17410
Minimum Input Voltage Requirements and Dropout Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot and the number of phases. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worstcase values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V SAG equation in the Transient Response section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP/IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VFB - VDROOP + VDIS VIN(MIN) = TOTAL 1 - TOTALh x t OFF(MIN)fSW + VCHG - VDIS + VDROOP where TOTAL is the total number of out-of-phase switching regulators, V FB is the voltage-positioning droop, VDIS and VCHG are the parasitic voltage drops in the discharge and charge paths (see the on-time one-shot parameter), tOFF(MIN) is from the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1.
Voltage Positioning and Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power dissipation requirements. The controller uses a transconductance amplifier to set the transient and DC output-voltage droop (Figure 2) as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.
Steady-State Voltage Positioning Connect a resistor (RFB) between FB and VOUT to set the DC steady-state droop (load line) based on the required voltage-positioning slope (RDROOP):
R FB = R DROOP R SENSEG m(FB)
where the effective current-sense resistance (RSENSE) depends on the current-sense method (see the Current Sense section), and the voltage-positioning amplifier's transconductance (Gm(FB)) is typically 1.2mS as defined
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43
Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies MAX17410
If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout Design Example: VFB = 1.4V fSW = 300kHz tOFF(MIN) = 400ns VDROOP = 3mV/A x 30A = 90mV VDROP1 = VDROP2 = 150mV (30A load) h = 1.5 and TOTAL = 2 1.4V - 90mV + 150mV VIN(MIN) = 2 x 1 - 2 x (0.4s x 1.5 x 300kHz) + 150mV - 150mV + 90mV = 4.96V Calculating again with h = 1 gives the absolute limit of dropout: 1.4V - 90mV + 150mV VIN(MIN) = 2 x 1 - 2 x (0.4s x 1.0 x 300kHz) + 150mV - 150mV + 90mV = 4.07V Therefore, VIN must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5.0V. 2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the V CC bypass capacitor and GNDS bypass capacitors. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. 4) Keep the high-current, gate-driver traces (DL_, DH_, LX_, and BST_) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 5) CSP_ and CSN_ connections for current limiting and voltage positioning must be made using Kelvin sense connections to guarantee the current-sense accuracy. 6) When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 7) Route high-speed switching nodes away from sensitive analog areas (CCI, FB, CSP_, CSN_, etc.).
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Refer to the MAX17410 evaluation kit specification for a layout example and follow these guidelines for good PCB layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC.
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Dual-Phase, Quick-PWM Controller for IMVP6+ CPU Core Power Supplies
4) Make the DC-DC controller ground connections as shown in the standard application circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the highpower components go; the power ground plane, where the GND pin and VDD bypass capacitor go; the master's analog ground plane where sensitive analog components, the master's GND pin, and VCC bypass capacitor go; and the slave's analog ground plane where the slave's GND pin and VCC bypass capacitor go. The master's GND plane must meet the GND plane only at a single point directly beneath the IC. Similarly, the slave's GND plane must meet the GND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the highpower output ground with a short metal trace from GND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.
MAX17410
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE 48 TQFN-EP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T4877+6 DOCUMENT NO. 21-0144
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 45
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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